Job Description
Roles and Responsibilities
- Digital design architecture
- Concept design, detailed design and RTL Coding using VHDL
- Requirement writing
- Synthesis, Place and Routing, Bit map generation
- STA and Timing closure
- Constraints writing
- Module level verification/development of testbenches
- Integration testing/onboard validation
- Protocols PCIe, SPI, ARINC 429, Mil 1553, Image processing.
- Experience in debugging VHDL/Verilog based design.
- Own and drive design related activities to provide technical support and proactively manage tasks to meet schedule goals.
- Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.
- Technical guidance to the junior engineers on design tasks.
- Must be ready for travel to abroad on need basis
- Minimum 1 year experience in MATLAB/Simulink
- Minimum 1 year experience in Coding/debugging VHDL RTL design.
- Minimum 1 years of experience with Questasim or similar advanced simulation tools.
- Minimum 1 year of experience in DO-254 verification process or similar.
- One year of experience in DOORS/Jama will be a plus.
- One year of experience in the control domain will be a plus.
Perks and Benefits
Group Term Life Insurance.
- Group Health Insurance.
- Group Personal Accident Insurance.
- Entitled for 22 days of vacation and 7 days of contingency leave annually.
- Employee scholar program.
- Work life balance.
- Car lease program.
- National Pension Scheme
- LTA
- Fuel & Maintenance /Driver wages
- Meal vouchers