Job Description
Job Function
The person will be responsible for driving and delivering the Power KPIs for next-generation SoCs for mobile and adjacent market products. The role will require the candidate to understand and work on all aspects of VLSI development including system power aspects, chip architecture, front end design, low power design, design for power and implementation. The person is also responsible for overseeing power-related deliveries to physical design and verification teams. Knowledge of PMIC design is an added advantage.
Skills/Experience
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15 to 18 years of solid experience in SoC design focusing on low power architecture and design including structural power checks, power-aware convergence
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Understand system-level use cases from a power perspective and map it to SoC level data flow to derive the power budgets and drive power optimizations
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Working knowledge of chipset architecture focusing on PMICs
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Bottoms up power estimations and roll-up including leakage, dynamic and clock tree power at the block level and SoC level
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Develop SoC Power specification for various chips
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Drive unified SoC low power methodologies scalable across various chips catering to various markets like Compute, Mobile, IOT, Auto etc.,
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Expertise in PHP, UPF and structural low power checks like CLP is a must.
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Good working knowledge on power-aware functional verification at both RTL and GLS level
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Needs to make effective and timely decisions, even with incomplete information.
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Should possess a strong understanding of low power design
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Provides direction, mentoring, and leadership to small to medium-sized groups.
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Should possess strong communication and leadership skills to ensure effective communication with Program Management or Engineering Management and group members
Responsibilities
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SoC power lead for Mobile and Adjacency chips
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Strong Digital design fundamentals and low power design expertise
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Good understanding of low power optimization techniques at all levels of design phase viz. architecture, microarchitecture, design and implementation
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Drive the SoC power milestones for various chips by managing all IP level UPF and other power collateral dependencies
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Strong influencing skills to drive power methodology solutions with external CAD vendors if needed
Education Requirements
Educational Qualification: MSEE strongly desired, BSEE required
Minimum Qualifications
Education:
Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems
Work Experiences:
8 years of Hardware Engineering experience or related work experience.
Certifications:
Skills:
Preferred Qualifications
Education:
Masters - Computer Science, Masters - Engineering, Masters - Information Systems
Work Experiences:
4 years in a technical leadership role with or without direct reports. ,4 years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc.,4 years experience utilizing schematic capture and circuit simulation software. ,4 years experience with circuit design (e.g., digital, analogue, RF). ,15 years of Hardware Engineering experience or related work experience.
Certifications:
Skills:
Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems