Job Description
Role
The team member will typically work on processors, controller architectures or ASICs. Proficient in chip/block level floorplanning, placement, clock tree synthesis, routing, RC extraction, STA, timing closure, IR/EM analysis and fix, DRC/LVS/ERC analysis and fix, sign-off and tape out activities with multiple metal layers
Requirements
- Minimum of 14 years of hands-on physical design implementation experience along with APR flow development and PPA analysis
- Advanced process technology nodes (6/7 nm preferred)
- Experience with Cadence layout tools (Innovus, Tempus, etc..) or Synopsys (ICC2, PrimeTime, etc).
- Stronghold on the fundamentals of digital electronics and microprocessors is necessary.
- Required soft skills – Customer orientation, English language proficiency, Good collaboration and interpersonal skills. Good analytical and Problem-solving skills along with strong ownership, commitment and time management.
- Bachelor’s or Masters with a relevant education is in the field of electronics and computer architecture
Preferred Skills:
- Strong verbal communication skills
- Cadence layout tools.
- Formal verification experience
- ESD - Need, Implement, Check mechanism - exposure to
- Digital electronics and microprocessors experience